Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

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Author:C. Pacha, O. Kessler, P. Glösekötter, K. F. Goser, W. Prost, A. Brennemann, U. Auer, F. J. Tegude
Parent Title (English):Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers
Document Type:Article
Year of Completion:2000
Year of first Publication:2000
Release Date:2019/01/11
First Page:7
Last Page:25
Faculties:Elektrotechnik und Informatik (ETI)
Publication list:Glösekötter, Peter
Licence (German):License LogoBibliographische Daten