Thresold Logic Circuit Design of Parallel Adders Using Resonant Tunneling Devices
| Author: | C. Pacha, U. Auer, C. Burwick, P. Glösekötter, A. Brennemann, W. Prost, F. J. Tegude, K. F. Goser |
|---|---|
| Parent Title (English): | IEEE Transactions on Very Larg Scale Integration (VLSI) Systems |
| Document Type: | Article |
| Language: | English |
| Year of Completion: | 2000 |
| Year of first Publication: | 2000 |
| Release Date: | 2019/01/11 |
| Volume: | October |
| First Page: | 558 |
| Last Page: | 572 |
| Faculties: | Elektrotechnik und Informatik (ETI) |
| Publication list: | Glösekötter, Peter |
| Licence (German): |  Bibliographische Daten |