TY  - JOUR
A1  - Pacha, C.
A1  - Kessler, O.
A1  - Glösekötter, P.
A1  - Goser, K. F.
A1  - Prost, W.
A1  - Brennemann, A.
A1  - Auer, U.
A1  - Tegude, F. J.
T1  - Parallel Adder Design with Reduced Circuit Complexity Using Resonant  Tunneling Transistors and Threshold Logic
JF  - Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers
Y1  - 2000
U6  - http://dx.doi.org/10.1023
SP  - 7
EP  - 25
ER  - 
TY  - CHAP
A1  - Pacha, C.
A1  - Glösekötter, P.
A1  - Goser, K. F.
A1  - Auer, U.
A1  - Prost, W.
A1  - Tegude, F. J.
T1  - Resonant Tunneling Transistors for Threshold Logic Circuit Applications
T2  - GLS-VLSI - 9th IEEE Great Lakes Symposium on VLSI
Y1  - 1999
SP  - 344
EP  - 345
CY  - Ann Arbor, MI
ET  - March 4-6
ER  - 
TY  - JOUR
A1  - Pacha, C.
A1  - Auer, U.
A1  - Burwick, C.
A1  - Glösekötter, P.
A1  - Brennemann, A.
A1  - Prost, W.
A1  - Tegude, F. J.
A1  - Goser, K. F.
T1  - Thresold Logic Circuit Design of Parallel Adders Using Resonant Tunneling Devices
JF  - IEEE Transactions on Very Larg Scale Integration (VLSI) Systems
Y1  - 2000
VL  - October
SP  - 558
EP  - 572
ER  - 
TY  - CHAP
A1  - Janßen, G.
A1  - Prost, W.
A1  - Auer, U.
A1  - Tegude, F.- J.
A1  - Pacha, C.
A1  - Glösekötter, P.
A1  - Goser, K. F.
A1  - van de Roer, T.
A1  - Foerster, A.
A1  - Malindretos, J.
A1  - Kelly, M. J.
T1  - Logic Circuits with Reduced Complexity based on Devices with Higher Functionality
T2  - Proc. 'Workshop on Semiconductor Advances for Future Electronics (SAFE)
Y1  - 1999
CY  - Mierlo, The Netherlands
ET  - Nov. 24-25
ER  - 
TY  - CHAP
A1  - Glösekötter, P.
A1  - Pacha, C.
A1  - Goser, K. F.
A1  - Wirth, G. I.
A1  - Prost, W.
A1  - Auer, U.
A1  - Agethen, M.
A1  - Tegude, F. J.
T1  - Digital Circuit Design Based on the Resonant-Tunneling-Hetero-Junction-Bipolar-Transistor
T2  - SBCCI
Y1  - 2000
CY  - Manaus, Brasil
ET  - Sept. 18-24
ER  -