TY  - CHAP
A1  - Rojas, I.
A1  - Anguita, M.
A1  - Pelayo, F. J.
A1  - Glösekötter, P.
A1  - Prieto, A.
T1  - CMOS implementation of RBF Neural Networks using Adaptive Baussian Radial Functions
T2  - Proceedings of the 6th International Conference on Microelectronics  for Neural Networks, Evolutionary & Fuzzy Systems (MicroNeuro'97)
Y1  - 1997
CY  - Dresden, Germany
ET  - September
ER  - 
TY  - CHAP
A1  - Pacha, C.
A1  - Glösekötter, P.
A1  - Goser, K. F.
T1  - Adiabatic Switching and Power Dissipation of Dynamic Resonant Tunneling Device Logic Circuits
T2  - 3rd Workshop on Innovative Circuits and Systems for Nano Elektronics, Nano-EL98
Y1  - 1998
PB  - Munich Paper C2/1-6
ET  - Sept. 5-6
ER  - 
TY  - CHAP
A1  - Glösekötter, P.
A1  - Kanstein, A.
A1  - Jung, S.
A1  - Goser, K. F.
T1  - Implementation of a RBF Network Based on Possibilistic Reasoning, ISSN 1089-6503
T2  - Proceedings of the 24th EUROMICRO conference
Y1  - 1998
SN  - 0-8186-8646-4
SP  - 677
EP  - 682
CY  - Västeras, Sweden
ET  - August 25-27
ER  - 
TY  - CHAP
A1  - Glösekötter, P.
A1  - Pacha, C.
A1  - Goser, K. F.
T1  - Associative Matrix for Nano-scale Integratd Circuits
T2  - 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems (MicroNeuro)
Y1  - 1999
SP  - 352
EP  - 358
PB  - IEEE Computer Society Press, Los Alamitos, CA
CY  - Granada, Spain
ET  - March
ER  - 
TY  - CHAP
A1  - Pacha, C.
A1  - Glösekötter, P.
A1  - Goser, K. F.
A1  - Auer, U.
A1  - Prost, W.
A1  - Tegude, F. J.
T1  - Resonant Tunneling Transistors for Threshold Logic Circuit Applications
T2  - GLS-VLSI - 9th IEEE Great Lakes Symposium on VLSI
Y1  - 1999
SP  - 344
EP  - 345
CY  - Ann Arbor, MI
ET  - March 4-6
ER  - 
TY  - CHAP
A1  - Janßen, G.
A1  - Prost, W.
A1  - Auer, U.
A1  - Tegude, F.- J.
A1  - Pacha, C.
A1  - Glösekötter, P.
A1  - Goser, K. F.
A1  - van de Roer, T.
A1  - Foerster, A.
A1  - Malindretos, J.
A1  - Kelly, M. J.
T1  - Logic Circuits with Reduced Complexity based on Devices with Higher Functionality
T2  - Proc. 'Workshop on Semiconductor Advances for Future Electronics (SAFE)
Y1  - 1999
CY  - Mierlo, The Netherlands
ET  - Nov. 24-25
ER  - 
TY  - JOUR
A1  - Pacha, C.
A1  - Auer, U.
A1  - Burwick, C.
A1  - Glösekötter, P.
A1  - Brennemann, A.
A1  - Prost, W.
A1  - Tegude, F. J.
A1  - Goser, K. F.
T1  - Thresold Logic Circuit Design of Parallel Adders Using Resonant Tunneling Devices
JF  - IEEE Transactions on Very Larg Scale Integration (VLSI) Systems
Y1  - 2000
VL  - October
SP  - 558
EP  - 572
ER  - 
TY  - JOUR
A1  - Pacha, C.
A1  - Kessler, O.
A1  - Glösekötter, P.
A1  - Goser, K. F.
A1  - Prost, W.
A1  - Brennemann, A.
A1  - Auer, U.
A1  - Tegude, F. J.
T1  - Parallel Adder Design with Reduced Circuit Complexity Using Resonant  Tunneling Transistors and Threshold Logic
JF  - Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers
Y1  - 2000
U6  - http://dx.doi.org/10.1023
SP  - 7
EP  - 25
ER  - 
TY  - CHAP
A1  - Glösekötter, P.
A1  - Pacha, C.
A1  - Goser, K. F.
T1  - Design of Arithmetic Circuits Using the RTBT
T2  - ITG-Fachbericht 162, Mikroelektronik für die Informationstechnik
Y1  - 2000
SN  - 3-8007-2586-X
SP  - 147
EP  - 150
ET  - Nov. 20-21
ER  - 
TY  - CHAP
A1  - Glösekötter, P.
A1  - Pacha, C.
A1  - Goser, K. F.
T1  - Threshold Logic Circuit Design using the RTBT
T2  - Kleinheubacher Berichte
Y1  - 2000
ET  - Sept. 25-29
ER  -