@incollection{PachaProstTegudeetal.2001,
  author    = {Pacha, C. and Prost, W. and Tegude, F. J. and Gl{\"o}sek{\"o}tter, P. and Goser, K. F.},
  title     = {Resonant Tunneling Device Logic: A Circuit Designer's Perspective},
  series = {European Conference on Circuit Theory and Design},
  booktitle = {European Conference on Circuit Theory and Design},
  edition   = {August 28-31},
  address   = {Espoo, Finland},
  year      = {2001},
  language  = {mul}
}
@incollection{PachaGloesekoetterGoseretal.1999,
  author    = {Pacha, C. and Gl{\"o}sek{\"o}tter, P. and Goser, K. F. and Auer, U. and Prost, W. and Tegude, F. J.},
  title     = {Resonant Tunneling Transistors for Threshold Logic Circuit Applications},
  series = {GLS-VLSI - 9th IEEE Great Lakes Symposium on VLSI},
  booktitle = {GLS-VLSI - 9th IEEE Great Lakes Symposium on VLSI},
  edition   = {March 4-6},
  address   = {Ann Arbor, MI},
  pages     = {344 -- 345},
  year      = {1999},
  language  = {en}
}
@article{PachaAuerBurwicketal.2000,
  author    = {Pacha, C. and Auer, U. and Burwick, C. and Gl{\"o}sek{\"o}tter, P. and Brennemann, A. and Prost, W. and Tegude, F. J. and Goser, K. F.},
  title     = {Thresold Logic Circuit Design of Parallel Adders Using Resonant Tunneling Devices},
  series = {IEEE Transactions on Very Larg Scale Integration (VLSI) Systems},
  volume    = {October},
  journal   = {IEEE Transactions on Very Larg Scale Integration (VLSI) Systems},
  pages     = {558 -- 572},
  year      = {2000},
  language  = {en}
}