@article{PachaKesslerGloesekoetteretal.2000,
  author    = {Pacha, C. and Kessler, O. and Gl{\"o}sek{\"o}tter, P. and Goser, K. F. and Prost, W. and Brennemann, A. and Auer, U. and Tegude, F. J.},
  title     = {Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic},
  series = {Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers},
  journal   = {Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers},
  doi       = {10.1023},
  pages     = {7 -- 25},
  year      = {2000},
  language  = {en}
}
@article{PachaAuerBurwicketal.2000,
  author    = {Pacha, C. and Auer, U. and Burwick, C. and Gl{\"o}sek{\"o}tter, P. and Brennemann, A. and Prost, W. and Tegude, F. J. and Goser, K. F.},
  title     = {Thresold Logic Circuit Design of Parallel Adders Using Resonant Tunneling Devices},
  series = {IEEE Transactions on Very Larg Scale Integration (VLSI) Systems},
  volume    = {October},
  journal   = {IEEE Transactions on Very Larg Scale Integration (VLSI) Systems},
  pages     = {558 -- 572},
  year      = {2000},
  language  = {en}
}
@incollection{GloesekoetterPachaGoseretal.2000,
  author    = {Gl{\"o}sek{\"o}tter, P. and Pacha, C. and Goser, K. F. and Wirth, G. I. and Prost, W. and Auer, U. and Agethen, M. and Tegude, F. J.},
  title     = {Digital Circuit Design Based on the Resonant-Tunneling-Hetero-Junction-Bipolar-Transistor},
  series = {SBCCI},
  booktitle = {SBCCI},
  edition   = {Sept. 18-24},
  address   = {Manaus, Brasil},
  year      = {2000},
  language  = {en}
}