TY  - JOUR
A1  - Pacha, C.
A1  - Auer, U.
A1  - Burwick, C.
A1  - Glösekötter, P.
A1  - Brennemann, A.
A1  - Prost, W.
A1  - Tegude, F. J.
A1  - Goser, K. F.
T1  - Thresold Logic Circuit Design of Parallel Adders Using Resonant Tunneling Devices
T2  - IEEE Transactions on Very Larg Scale Integration (VLSI) Systems
Y1  - 2000
UR  - https://www.hb.fh-muenster.de/opus4/frontdoor/index/index/docId/8174
VL  - October
SP  - 558
EP  - 572
ER  -