TY  - JOUR
A1  - Pacha, C.
A1  - Kessler, O.
A1  - Glösekötter, P.
A1  - Goser, K. F.
A1  - Prost, W.
A1  - Brennemann, A.
A1  - Auer, U.
A1  - Tegude, F. J.
T1  - Parallel Adder Design with Reduced Circuit Complexity Using Resonant  Tunneling Transistors and Threshold Logic
T2  - Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers
Y1  - 2000
UR  - https://www.hb.fh-muenster.de/opus4/frontdoor/index/index/docId/8175
SP  - 7
EP  - 25
ER  -